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These location descriptions assume that you are looking at the board so that the expansion slots are running from left to right, with the keyboard connector closest to the side facing you.
Power good selector
JP9 is nearest to the bottom left hand side of the board, and this controls the "Power Good Selection"
1&2 connected enables the internal power fail detect circuit
2&3 connected assumes external power-good function
Front panel connectors
J1, J2, J3, J4 and J5 (note!! Jx, NOT JPx) are located together on the left had side of the board, roughly half way up.
J1 is the speaker connector
J2 is the keyboard lock
J3 is the turbo LED (pin1=+5V)
J4 is the hardware reset
J5 is the turbo speed selection
Basically the 1&2 positions overlay the SIP banks on top of the DIP banks, and the 2&3 positions add the SIP banks after (ie, as banks 2 & 3) the DIP banks.
Display adapter jumper JP8
Located directly left of the keyboard socket, just above the keyboard interface IC.
1&2 Monochrome
2&3 Colour
Battery selector JP7
Jumper JP7 selects where the battery is located (onboard or external); it is located just above and to the right of JP8.
1&2 External battery (connected to J6)
2&3 onboard battery
Battery connector J6
Pin 1 +6V
Pin 2 Not used
Pin 3 Not used
Pin 4 GND
Memory configurations:
JP1-6 are located between the SIP sockets and the DIP RAM sockets towards the top left of the board. (Again, note, these are JPx, not Jx)
A note on memory - the DIP RAM sockets are arranged into bank 0 and bank 1 - bank 0 consists of the six sockets arranged in a rectangular format - bank 1 has a "wonky" arrangement.
| Total memory | Arrangement | JP1 | JP2 | JP3 | JP4 | JP5 | JP6 |
| 512k | DIP Bank 0 = 44256x4+41256x2 | 1&2 | 1&2 | 1&2 | 1&2 | 1&2 | 1&2 |
| 640k | SIP Bank 0 = 41256 module x 2
DIP Bank 0 = 44256x4 + 41256x2 |
1&2 | 1&2 | 1&2 | 1&2 | 1&2 | 1&2 |
| 1MB | SIP Bank 0 = 41256 module x 2
DIP Bank 0 = 44256x4 + 41256x2 |
1&2 | 1&2 | 1&2 | 1&2 | 1&2 | 1&2 |
| 1.5MB | DIP Bank 0 = 44256x4 + 41256x2
DIP Bank 1 = 44256x4 + 41256x2 SIP Bank 0 = 41256 module x 2 |
2&3 | 2&3 | 2&3 | 2&3 | 2&3 | 2&3 |
| 2MB | DIP Bank 0 = 44256x4 + 41256x2
DIP Bank 1 = 44256x4 + 41256x2 SIP Bank 0 = 41256 module x 2 SIP Bank 1 = 41256 module x 2 |
2&3 | 2&3 | 2&3 | 2&3 | 2&3 | 2&3 |
| 3MB | DIP Bank 0 = 44256x4 + 41256x2
DIP Bank 1 = 44256x4 + 41256x2 SIP Bank 0 = 411000 module x 2 |
2&3 | 2&3 | 2&3 | 2&3 | 2&3 | 2&3 |
| 4MB | SIP Bank 0 = 411000 module x 2
SIP Bank 1 = 411000 module x 2 |
1&2 | 1&2 | 1&2 | 1&2 | 1&2 | 1&2 |
| 5MB | DIP Bank 0 = 44256x4 + 41256x2
DIP Bank 1 = 44256x4 + 41256x2 SIP Bank 0 = 411000 module x 2 SIP Bank 1 = 411000 module x 2 |
2&3 | 2&3 | 2&3 | 2&3 | 2&3 | 2&3 |
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